1. Field of the Invention
The present invention is related to the field of phase window test circuitry and methods.
2. Background Art
Phase window test circuitry and methods are used to measure the phase window of a data separator utilized in disk drive systems. Data separators are used in data disk systems to separate data signals and clock signals from an analog signal read from the disk media (hereinafter referred to as the read signal). A phase-locked loop (PLL) circuit is implemented in the data separator to produce a clock signal equal in frequency to the data rate of the read signal obtained from the disk media. The PLL circuit acquires the nominal frequency of the read signal and tracks deviations in its nominal frequency, thereby producing an output clock frequency that varies according to deviations of the reference frequency (frequency of the read signal).
In order to track the read signal frequency, the PLL circuit compares the phase of the reference signal to the phase of the PLL output signal. The difference in phase between the two frequencies produces an error signal that drives a voltage controlled oscillator (VCO) of the PLL, thereby forcing the VCO output frequency to follow changes in the reference frequency. The phase "window" of the phase detector defines the range of phase values that the phase detector detects correctly.
PLL circuits implemented in data separators are produced on integrated circuits (IC). Data separator circuits employing phase-locked loops require acquisition circuitry that is well centered within its phase detection window. As a result, a phase window test must be performed on such devices. Automatic test equipment (ATE) is commonly used to test integrated circuits and is generally implemented with digital hardware. However, a need exists for an accurate, digital method of phase window testing suitable for use with ATE systems for testing PLLs implemented in data separators.
FIG. 1 is a block diagram of a PLL 170 of the type embodied in a data separator. The PLL 170 comprises a phase detector 110, charge pump 120, lowpass filter 130 and VCO 140. Reference signal 150 is provided to a first input of phase detector 110. A pump up signal 112 produced at a first output of phase detector 110 is provided to a first input of charge pump 120. A pump down signal 114 produced at a second output of phase detector 110 is provided to a second input of charge pump 120. The output signal 122 of charge pump 120 is coupled to the input of lowpass filter 130. The output voltage signal 132 of lowpass filter 130 is coupled to the input of VCO 140. VCO 140 provides VCO output signal 160 which is feedback coupled to a second input of phase detector 110.
The reference signal 150 has a nominal frequency, f.sub.REF, that is provided to phase detector 110. The phase detector compares frequency f.sub.REF to the frequency f.sub.VCO of the VCO output signal 160 provided to the second input of phase detector 110. Phase detector 110 generates one of two signals pump up signal 112 or pump down signal 114, indicating the difference in phase between reference signal 150 and VCO output signal 160. Initially, the frequency f.sub.VCO of VCO output signal 160 is not equal to the frequency f.sub.REF of the reference signal 1150 and the phase detector produces a phase error signal. The phase error signal is applied to charge pump 120 and may be either pump up signal 112 or pump down signal 114. Pump up signal 112 and pump down signal 114 indicate the difference in phase by which reference signal 150 leads or lags the phase of VCO output signal 160, respectively.
Pump up signal 112 and pump down signal 114 are coupled to the inputs of charge pump 120. Charge pump 120 is well-known in the art and is, therefore not shown in greater detail. However, for purposes of completeness, a typical embodiment is considered comprising a p-type FET and an n-type FET having drains coupled in series that provides an output current. Charge pump 120 produces an output current 122 in response to pump up signal 112 and pump down signal 114 generated by phase detector 110. Thus, pump up signal 112 and pump down signal 114 act to provide current pulses for output signal 112 of charge pump 120. This is affected by transferring charge through transistor action in response to the pump up and pump down signals 112-114, respectively.
The output signal 122 of charge pump 120 is provided to lowpass filter 130. Lowpass filter 130 receives output signal 122 of charge pump 120, thereby producing analog output signal 132 that controls VCO 140. The voltage level of output signal 132 sets the frequency f.sub.VCO of VCO output signal 160, thereby adjusting the value of frequency f.sub.VCO. The new value of frequency f.sub.VCO of the VCO output signal 160 is applied to the second input of phase detector 110 which further changes the phase error signal produced by phase detector 110. Phase detector 110 generates a train of pulses provided to charge pump 120, producing current pulses output by charge pump 120 and filtered by lowpass filter 130 so that VCO 140 tracks changes in the reference frequency. Thus, the difference in phase of reference signal 150 and VCO output signal 160 is used in the PLL 170 to control the VCO output signal 160 so that frequency f.sub.VCO of VCO output signal 160 is equal to frequency f.sub.REF of reference signal 150 through feedback action.
Once the frequency f.sub.VCO of VCO output signal 160 becomes equal to, or captures, the frequency f.sub.REF of reference signal 150, PLL 170 tracks changes in frequency of reference signal 150 producing an equal frequency for VCO output signal 160 over a range of frequencies referred to as the lock range. The lock range is the range of phase values for the difference in phase between reference signal 150 and locked VCO output signal 160 that produces an appropriate voltage level at the output of lowpass filter 130, thereby forcing frequency f.sub.VCO of VCO output signal 160 to track frequency f.sub.REF of reference signal 150.
A first prior art method for measuring the phase window of PLL 170 shown in FIG. 1 is an analog method. In this technique, a fixed frequency data pattern (hereinafter referred to as reference signal 150) is applied to the input of PLL 170 while the analog voltage signal 132 output on the pins of the lowpass filter 130 in PLL 170 is monitored. The PLL 170 captures fixed frequency reference signal 150 and tracks its frequency f.sub.REF. Once PLL 170 has captured fixed frequency reference signal 150 and settled, a single data bit in the fixed frequency reference signal 150 is shifted from its initial position in the center of the phase window. The single data bit is shifted so that its phase leads or lags its initial position. As the selected data bit is shifted to lead or lag in phase, the analog voltage on the pins of lowpass filter 130 of PLL 170 changes accordingly. Thus, if the selected bit is shifted so that it is leading its initial position, the analog voltage 132 output by lowpass filter 130 increases. Similarly, if the shifted data bit is lagging in phase, a corresponding decrease in the analog voltage 132 of lowpass filter 130 occurs.
FIG. 2 is a timing diagram for an early bit illustrating reference signal 150, VCO output signal 160, pump up signal 112, pump down signal 114 and analog voltage signal 132 generated by lowpass filter 130. An early bit is a single data bit of the fixed frequency reference signal 150 that is shifted in phase so that it leads its initial position. Dotted lines 224 and 228 denote the period 1/f.sub.REF of reference signal 150 and 1/3 cell delay 210 is shown. Similarly, dotted lines 224 and 226 denote the period 1/f.sub.VCO of VCO output signal 160. As shown in FIG. 2, the frequency f.sub.VCO of VCO output signal 160 is three times greater than frequency f.sub.REF of reference signal 150 in the present example. The duration of 1/3 cell delay 210 of reference signal 150 is equal to one half of the period 1/f.sub.VCO of VCO output signal 160.
An unshifted data bit 240 shown in FIG. 2 occurs at rising edge 240A of reference signal 150. Dotted line 228 indicates that the rising edge 240A of data bit 240 is exactly in phase with the rising edge 250A of data bit 250 of VCO output signal 160. An early bit is illustrated by data bit 214 which leads its initial position in phase. Initially, data bit 214 of reference signal 150 and data bit 230 of VCO output signal are in phase, so that rising edge 214A of data bit 214 is aligned with rising edge 230A of data bit 230. However, data bit 214 is shifted to have a leading phase with respect to its initial position which is referenced by rising edge 230A of data bit 230. As shown in FIG. 2, the early bit is indicated by rising edge 214A of data bit 214 which leads rising edge 230A of VCO output signal 160.
Phase detector 110 determines the difference in phase between reference signal 150 and VCO output signal 160 by comparing the rising edge, of a pulse during a cycle of reference signal 150 with the rising edge of a pulse during every third cycle of VCO output signal 160. This is illustrated in FIG. 2, for an early bit, by rising edge 214A of reference signal 150 and rising edge 230A of VCO output signal 160. Data bit 214 of reference signal 150 is shifted relative to its initial position so that it is leading in phase. The initial position of data bit 214 corresponds to rising edge 230A of VCO output signal 160. The rising edge 214A of shifted data bit 214 is leading rising edge 230A of VCO output signal 160 by nearly 180 degrees. In response to this phase difference, phase detector 110 produces a corresponding pulse 216 in pump up signal 112 provided to charge pump 120 shown in FIG. 1. Pulse 216 of pump up signal 112 increases the output current 122 of charge pump 120 thereby resulting in an increased, positive voltage for analog voltage signal 132 produced by lowpass filter 130. The analog voltage level 220 of analog voltage signal 132 due to pulse 216 of pump signal 112 is indicated by a solid line.
Analog voltage level 220 of analog voltage signal 132 corresponds to the maximal leading phase of the phase window for phase detector 110. Leading edge 212A (represented by a dashed lined) indicates that data bit 214 is shifted slightly beyond a leading phase of 180 degrees. In response to the leading phase of rising edge 212A of reference signal 150, phase detector generates a pulse 218 in pump down signal 114 that is indicated by a dashed line in FIG. 2. In this case, no pulse is produced on pump up signal 112. Pulse 218 of pump down signal 114 produces an inversion in polarity of analog voltage signal 132 at the output of lowpass filter 130. The negative analog voltage level 222 of analog voltage signal 132 due to pulse 218 of pump down signal 114 is indicated by a corresponding dashed line. Thus, the leading phase of data bit 214 of reference signal 150 corresponding to inverted voltage level 222 of analog voltage signal 132 produced by lowpass filter 130 demarks one edge of the phase window for phase detector 110 of PLL 170.
FIG. 3 is a timing diagram for a late bit illustrating reference signal 150, VCO output signal 160, pump up signal 112, pump down signal 114 and analog voltage signal 132 generated by lowpass filter 130. A late bit is a single data bit of the fixed frequency reference signal 150 that is shifted in phase so that it lags its initial position. Dotted lines 224 and 228 denote the period 1/f.sub.REF of reference signal 150 and 1/3 cell delay 210 is shown. Similarly, dotted lines 224 and 226 denote the period 1/f.sub.VCO of VCO output signal 160. As shown in FIG. 3, the frequency f.sub.VCO of VCO output signal 160 is three times greater than frequency f.sub.REF of reference signal 150 in the present example. The duration of 1/3 cell delay 210 of reference signal 150 is equal to one half of the period 1/f.sub.VCO of VCO output signal 160.
An unshifted data bit 340 shown in FIG. 3 occurs at rising edge 340A of reference signal 150. Dotted line 228 indicates that the rising edge 340A of data bit 340 is exactly in phase with the rising edge 350A of data bit 350 of VCO output signal 160. A late bit is illustrated by data bit 314 which lags its initial position in phase. Initially, data bit 314 of reference signal 150 and data bit 330 of VCO output signal are in phase, so that rising edge 314A of data bit 314 is aligned with rising edge 330A of data bit 330. However, data bit 314 is shifted to have a lagging phase with respect to its initial position which is referenced by rising edge 330A of data bit 330. As shown in FIG. 3, the late bit is indicated by leading edge 314A of data bit 314 which lags rising edge 330A of VCO output signal 160.
Phase detector 110 compares the difference in phase between reference signal 150 and VCO output signal 160 by monitoring the rising edge of a pulse during a cycle of reference signal 150 with the rising edge of a pulse during every third cycle of VCO output signal 160. This is illustrated in FIG. 3, for a late bit, by rising edge 314A of reference signal 150 and rising edge 330A of VCO output signal 160. Data bit 314 of reference signal 150 is shifted relative to its initial position so that it is lagging in phase. The initial position of data bit 314 corresponds to rising edge 330A of VCO output signal 160. The rising edge 314A of shifted data bit 314 is lagging rising edge 330A of VCO output signal 160 by nearly 180 degrees. In response to this phase difference, phase detector 110 produces a corresponding pulse 316 in pump down signal 114 provided to charge pump 120 shown in FIG. 1. Pulse 316 of pump up signal 112 decreases the output current 122 of charge pump 120, thereby resulting in a negative voltage for analog voltage signal 132 produced by lowpass filter 130. The analog voltage level 320 of analog voltage signal 132 due to pulse 316 of pump signal 112 is indicated by a solid line.
Analog voltage level 320 of analog voltage signal 132 corresponds to the maximal lagging phase of the phase window for phase detector 110. Lagging edge 312A (represented by a dashed lined) indicates that data bit 314 is shifted slightly beyond a lagging phase of 180 degrees. In response to the lagging phase of rising edge 312A of reference signal 150, phase detector generates a pulse 318 in pump up signal 112 that is indicated by a dashed line in FIG. 3, while no pulse is produced on pump down signal 114. Pulse 318 of pump up signal 112 produces an inversion in polarity of analog voltage signal 132 at the output of lowpass filter 130, The inverted analog voltage level 322 of analog voltage signal 132 due to pulse 318 of pump up signal 112 is indicated by a corresponding dashed line. Thus, the lagging phase of data bit 314 of reference signal 150 corresponding to inverted voltage level 322 of analog voltage signal 132 produced by lowpass filter 130 demarks the second edge of the phase window for phase detector 110 of PLL 170.
If the selected data bit 214 (314) is shifted past-the edges of the phase window as shown in FIGS. 2 and 3, the polarity of analog voltage signal 132 of lowpass filter 130 is inverted. The polarity change marks the upper and lower edges of the phase window and the phase window is measured in this manner. However, this prior art method has the disadvantage that it is not easily implemented in ATE systems since it is an analog method. As stated above, ATE systems are inherently digital systems and, therefore are not suitable for implementation with such an analog method.
A second prior art method for testing the phase window of a PLL measures the pulse width of the 1/3 cell delay signal at a monitor pin. Since the 1/3 cell delay is the primary defining element of the phase window circuit, measuring its pulse width provides an indication of the phase window accuracy. This method can be implemented with ATE systems due to its digital nature. However, there are two disadvantages to this prior art method. First, the monitor point is difficult to measure accurately at high data rates. The high data rate of the read signal (i.e., 48 Megabits/sec) provided to the data separator produces very narrow pulse widths that are difficult to measure. Also, capacitive loading at the monitor point due measurement equipment produces skewed pulses that further distort such measurements. Finally, delays inherent in the data separator circuitry further produce asymmetries in the measured data pulses.
Thus, a need exists for a digital method of accurately testing the phase window of a phase detector employed in a phase-docked loops that can be implemented in ATE systems.